1. Field of Invention
The present invention relates to a method of producing channel stoppers for integrated circuits and more particularly to a method for forming metal silicide channel stoppers for dielectric filled deep trench isolated devices.
2. Description of the Prior Art
Channel inversion is one of the most common and important problem in the field of oxide-isolated or oxide-passivated semi-conductor integrated circuits manufacturing. The problem typically arises when two N (or N+) type, adjacent but not contiguous, regions formed in a P.sup.- type silicon substrate, are passivated by an oxide layer. Usually occurring at the interface between the P type silicon and the passivating oxide, channel inversion may result from a wide variety of factors: presence of certain impurities such as sodium ions in the oxide, influence of an overlying metallization pattern, affinity of boron dopants to segregate into an silicon dioxide layer, . . . , etc. Channel inversion causes those regions to be electrically connected by a N type channel formed at the surface of said P.sup.+ type silicon substrate. In many instances, this connection is not desired and results in degradation of electrical performances of devices.
More recent trends in micro-electronics, which capitalize both, on dielectric isolation and general use of lightly doped substrates, make advanced devices more sensitive to channel inversion problems caused by the third factor mentioned above (affinity of boron dopants to segregate), for reasons which will be briefly commented thereafter.
According to that particular type of dielectric isolation, patterns of dielectrically filled trenches extending from the surface of the integrated circuit to the interior thereof, are advantageously used to isolate the devices (one bipolar transistor from another bipolar transistor) or portions of the devices (the base region from the collector region in a bipolar transistor). Because this technique considerably increases the integration density, it is now widely practiced.
On the other hand, silicon wafers have lightly doped substrates in order to significantly reduce collector-substrate capacitances, which in turn increases the operating frequencies of the devices.
In a typical example of manufacturing such advanced integrated circuits, the initial structure is a P.sup.+ substrate having a blanket (or discrete) N.sup.+ subcollector and a N.sup.+ epitaxial layer thereon. Using standard photo lithographic and Reactive Ion Etching (RIE) techniques, trenches are formed through the N.sup.+ epitaxial layer into the P.sup.+ substrate. Following etching, a thin (50-150 nm) thermal SiO.sub.2 layer is regrown in trenches to cover the trench sidewalls. While SiO.sub.2 regrowth is optional, it is extensively practiced. It is used as an underlying layer for the subsequent dielectric to be filled in the trenches. The growth of thin oxide layer can be detrimental to the distribution of dopants in the underlying silicon, near the oxide silicon interface, principally with P.sup.+ type silicon. Unlike phosphorous atoms which have the the tendancy to pile up or accumulate on the silicon side of the interface (so called snow-plow effect), boron has a stronger affinity for silicon dioxide than for silicon. Thus, during oxide growth, the concentration of boron near the surface of said P.sup.- substrate tends to decrease because migration of boron atoms into silicon dioxide. As a result, there does exist a very thin N.sup.- type inverted layer superficially in the P.sup.- substrate at the bottom of the trench. Therefore, following SiO.sub.2 regrowth, a standard ion implantation is conducted, and boron is implanted into trenches to form P.sup.+ channel stopper regions at the bottom of the trenches. The ion implantation is highly directional in the vertical direction and is performed at .about.30 keV to provide a boron concentration of .about.1.times.10.sup.17 at/cm.sup.3. More often than not, the sidewalls of the trenches receive a Si.sub.3 N.sub.4 barrier layer before the trenches be filled either with SiO.sub.2 (by Chemical Vapor Deposition) or polyimide (by spinning). The process is completed by the conventional formation of active and passive devices until the whole structure is achieved.
The primary function of a channel stopper is, of course, to prevent undesirable effects caused by channel inversion, and it may have only this function as clearly mentioned for example by S. Magdo, IBM Technical Disclosure Bulletin, volume 24, No. 7B, December 1981, pages 3841 through 3843 (ref.1). In this disclosure, after the channel stoppers have been formed, the trenches are filled with oxide.
However in others applications, the channel stopper may also play the additional role of a buried substrate contact. This technique is described for example by S. A. Abbas et al, IBM Technical Disclosure Bulletin, Vol. 25, No. 12, May 1983, pages 6611 through 6614 (ref.2) and J. S. Basi et al, IBM Technical Disclosure Bulletin, volume 25, No. 8, January 1983, pages 4405 and 4406 (ref.3). The former article describes the formation of a polysilicon buried conductor for reach through to the P substrate for ohmic electrical contact thereto. Once the trenches have been opened and channel stoppers have been formed, trenches are protected with an insulating layer. Then, the bottom of the trench is opened to expose the channel stopper region and, a thin polysilicon layer is CVD deposited, providing a contact with the substrate. In the latter article, the substrate contact is made by shorting the subcollector to the channel stopper with a platinum silicide lining, and then to the top metallurgy via the collector reach-through diffusion. In Basi et al, the platinum silicide acts only to provide an ohmic contact to the P.sup.+ channel stopper.
Both methods do not provide satisfactory substrate resistance as it will be understood thereafter.
In general, the two functions of the channel stopper i.e. prevention of channel inversion and buried substrate contact, are simultaneously used in a silicon chip. A channel stopper is present at the bottom of all trenches, but only some of them will be used as a buried substrate contact.
Unfortunately, formation of said conventional channel stoppers makes an extra ion implantation step necessary. On the other hand, device structures isolated by filling deep trenches with a dielectric material, generally exhibit a problem of high substrate resistance due to the relatively low doping of the channel stop implant in the bottom of the trenches. The channel stop implant dose cannot be increased significantly above .about.1.0.times.10.sup.13 ions/cm.sup.2 of .sup.11 B.sup.+ without inducing emitter to collector shorts of lateral PNP transistors, butting the trench or between the P base region of an NPN transistor and a spaced apart P base resistor bed. In both cases this P to P leakage is caused by channel inversion of the epitaxial layer at the top of the trench due to undesired introduction of P dopants during the implantation step.
Another reason of limiting the dose is to avoid generation of dislocations. In addition, due to this doping limitation of the channel stop, the prevention of channel inversion effect is not satisfactory when commercially available polyimides are used. Most of them are not pure but contain undesired contaminants.